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74AC241 * 74ACT241 Octal Buffer/Line Driver with 3-STATE Outputs
November 1988 Revised March 2005
74AC241 * 74ACT241 Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The AC/ACT241 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus-oriented transmitter or receiver which provides improved PC board density.
Features
s ICC and IOZ reduced by 50% s Non-inverting 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s ACT241 has TTL-compatible inputs
Ordering Code:
Order Number 74AC241SC 74AC241SJ 74AC241MTC 74AC241PC 74ACT241SC 74ACT241SJ 74ACT241MTC 74ACT241PC Package Number M20B M20D MTC20 N20A M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Pin Descriptions
Pin Names OE1 OE2 I0-I7 O0-O7 Description 3-STATE Output Enable Input 3-STATE Output Enable Input (Active HIGH) Inputs Outputs
Truth Tables
Inputs OE1 In L H X Inputs OE2 H H L
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance FACT is a trademark of Fairchild Semiconductor Corporation.
Outputs (Pins 12, 14, 16, 18) L H Z Outputs In L H X (Pins 3, 5, 7, 9) L H Z
Connection Diagram
L L H
(c) 2005 Fairchild Semiconductor Corporation
DS009942
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74AC241 * 74ACT241
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI
0.5V to 7.0V 20 mA 20 mA 0.5V to VCC 0.5V 20 mA 20 mA 0.5V to VCC 0.5V r50 mA r50 mA 65qC to 150qC
140qC
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ('V/'t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate ('V/'t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
0.5V VCC 0.5V
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO
0.5V VCC 0.5V
40qC to 85qC
DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IN (Note 4) IOZ Maximum Input Leakage Current Maximum 3-STATE Leakage Current IOLD IOHD ICC (Note 4) Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 4.0 5.5 0.002 0.001 0.001 TA Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36
25qC
TA
40qC to 85qC
2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4
Guaranteed Limits
Units VOUT V
Conditions 0.1V
or VCC 0.1V VOUT 0.1V
V
or VCC 0.1V
V
IOUT VIN
50 PA
VIL or VIH
2.46 3.76 4.76 0.1 0.1 0.1 V V
IOH IOH IOH IOUT VIN
12 mA 24 mA 24 mA (Note 2)
50 PA VIL or VIH 12 mA 24 mA 24 mA (Note 2) VCC, GND VIL, VIH VCC, GND VCC, GND 1.65V Max 3.85V Min VCC or GND
0.44 0.44 0.44 V
IOL IOL IOL VI VI VO
r0.1 r0.25
r1.0 r 2.5
75
PA PA
mA mA
VI (OE)
VOLD VOHD VIN
75
40.0
PA
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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2
74AC241 * 74ACT241
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 6) Maximum Quiescent Supply Current
Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
TA Typ 1.5 1.5 1.5 1.5 4.49 5.49
25qC
2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86
TA
40qC to 85qC
2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44
Guaranteed Limits
Units V V V VOUT VOUT IOUT VIN V IOH IOH V IOUT VIN
Conditions 0.1V 0.1V
or VCC 0.1V or VCC 0.1V
50 PA
VIL or VIH
24 mA 24 mA (Note 5)
50 PA VIL or VIH 24 mA 24 mA (Note 5) VCC, GND VIL, VIH VCC, GND VCC 2.1V 1.65V Max 3.85V Min VCC
0.001 0.001
0.1 0.1 0.36 0.36
V
IOL IOL VI VI VO VI
5.5 5.5 5.5 5.5 5.5 5.5 0.6
r0.1 r0.25
r1.0 r2.5
1.5 75
PA PA
mA mA mA
VOLD VOHD VIN or GND
75
4.0 40.0
PA
AC Electrical Characteristics for AC
VCC Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Data to Output Propagation Delay Data to Output Output Enable Time Output Enable Time Output Disable Time Output Disable Time (V) (Note 7) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Note 7: Voltage Range 3.3 is 3.3V r 3.3V Voltage Range 5.0 is 5.0V r 0.5V
TA CL Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.0 1.5 1.5 1.5
25qC
50 pF Typ 6.0 5.0 6.0 4.5 6.5 5.5 7.0 5.5 8.0 6.5 7.0 6.0 Max 9.0 7.0 9.0 7.0 12.5 9.0 12.0 9.0 12.0 10.0 12.5 10.0
TA
40qC to 85qC
CL 50 pF Max 10.0 7.5 10.5 7.5 13.0 9.5 13.0 9.5 12.5 10.5 13.0 10.5 ns ns ns ns ns ns Units
Min 1.5 1.0 1.0 1.0 1.0 1.0 1.5 1.0 2.0 1.0 1.0 1.0
3
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74AC241 * 74ACT241
AC Electrical Characteristics for ACT
VCC Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Data to Output Propagation Delay Data to Output Output Enable Time Output Enable Time Output Disable Time Output Disable Time 5.0 5.0 5.0 5.0 1.5 1.5 1.5 2.0 6.0 7.0 8.0 7.0 9.0 10.0 10.5 10.5 1.0 1.5 1.5 1.5 10.0 11.0 11.5 11.5 ns ns ns ns 5.0 1.5 7.0 9.0 1.5 10.0 ns (V) (Note 8) 5.0 Min 1.5 TA CL
25qC
50 pF Typ 6.5 Max 9.0
TA
40qC to 85qC
CL 50 pF Max 10.0 ns Units
Min 1.5
Note 8: Voltage Range 5.0 is 5.0V r 0.5V
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 45.0 Units pF pF VCC VCC OPEN 5.0V Conditions
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74AC241 * 74ACT241
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
5
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74AC241 * 74ACT241
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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6
74AC241 * 74ACT241
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
7
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74AC241 * 74ACT241 Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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